With the slowdown of Moore's law, the DRAM process has also entered the technical bottleneck period, and the expansion speed of DRAM has slowed significantly. Therefore, 3D DRAM has become a new path for storage manufacturers to break through the higher limit of DRAM technology. Recently, according to Korean media The ELEC, Samsung Electronics has formed a development team in its semiconductor research center to mass produce 4F2 DRAM. The goal of the development team is to apply the 4F2 DRAM storage unit to the DRAM process below 10 nanometers, and at the same time, it solves the problem of current technology facing the limit of scratching lines.
The reason for the slowdown in DRAM process breakthroughs is the simple structure of the storage unit -composed of a capacitor for storing charge and a transistor for access capacitors. To solve the contradiction between the slowdown of DRAM's expansion and the demand for large capacity, the main solution of the industry is currently subverting this structure, while adding some special materials to promote DRAM process innovation.
Earlier, the industry mainly increased the density of DRAM chips by reducing the width of the route. The smaller the width of the line, the more the transistor, the higher the integration, the lower the power consumption, and the faster the speed. Although this method does have a certain effect, after the line width enters 10nm, the problem of physical restrictions such as power leakage and interference of capacitors follows.
Of course, the industry has also introduced new materials and new equipment such as HIGH-K materials and extremely ultraviolet (EUV) equipment to solve this problem. However, in the manufacture of 10nm or more advanced small chips, some of the existing technologies can no longer overcome DRAM physical limitations. With the increasing contradiction between DRAM's technical technology and insufficient supply of DRAM, 2D DRAM risen to 3D DRAM has gradually become a consensus for the industry's pursuit of technological breakthroughs.
The 3D DRAM is a new type of storage method that stacked the storage unit (Cell) to the top of the logical unit, so as to achieve higher capacity in the unit wafer area. In principle, 3D DRAM can effectively solve the current dilemma of plane DRAM. At the same time, in terms of cost, the 3D stack technology used by 3D DRAM will achieve reusable use of storage capacitors, which can effectively reduce unit costs. It can be seen that DRAM's development from traditional 2D to 3D three -dimensional will be the future development trend.
Recently, according to the foreign media "Businesskorea", Samsung's main semiconductor leader recently stated at the semiconductor meeting that is accelerating the commercialization of 3D DRAM, and 3D DRAM is a way to overcome DRAM's physical limitations. It will change the game of the memory industry rule. At the same time, 3D DRAM is considered the future growth momentum of the semiconductor industry.
Since 2022, the depression of the electronic consumer market has allowed the memory market to enter the "cold winter", but the demand for memory in other fields such as automotive electronics and AI servers is still strong, especially the demand for high -performance storage such as HBM brought by ChatGPT will accelerate the acceleration. DRAM 3D development. TrendForce Ji State Consultation predicts that AI demand continues to drive the growth of HBM memory, and it is estimated that the compound annual growth rate of HBM markets from 2023 to 2025 is expected to grow to more than 40 ~ 45%.
The ELEC reports that if the structure of the Samsung 4F2 DRAM storage unit is successful, compared with the existing 6F2DRAM storage unit structure without changing the node, the chip DIE area can be reduced by about 30%. limit. The 4F2 structure is a unit structure technology that the DRAM industry failed to commercialize about 10 years ago. It is said that the process is quite difficult. Data show that 6F2 can reduce the area by 25-30%compared with 8F2.
It is reported that at present, the industry has the design of 8F2 and 6F2 DRAM units, including the unit including 1T (crystal tube) and 1C (capacitor). This 1T+1C unit design will be used for the DRAM unit design of several generations of DRAM in the future. However, due to the restrictions of process and layout, DRAM manufacturers have been developing the 4F2 unit structure, such as 1T DRAM or a capacitor DRAM prototype, as one of the next candidates for extended DRAM technology.
At the 2021 IEDM, the team of Researcher Li Ling Institute of Microelectronics Institute of the Chinese Academy of Sciences and the Huawei/Hisilicon team first proposed a new CAA. This structure effectively reduces the area of the device and supports multi-layer stacks. By directly connecting the upper and lower CAA devices, the size of each storage unit can be reduced to 4F2, which makes Igzo-DRAM have a density advantage.
In January 2023, Academician Liu Ming team of the Microelectronics Key Laboratory of the Institute of Microelectronics of the Chinese Academy of Sciences studied the impact of the second -layer device stacking the front layer process of the front layer of the front layer on the basis of the vertical ring channel structure (CAA) Igzo FET. The reliability of CAA IGZO FET in the 2T0C DARM application.